Biological implants, radio frequency identification device (“RFID”) tags, and smart credit cards utilize low bit-rate short distance communications. Power consumption is of utmost importance in such applications. Recently there has been a lot of attention to the development of implantable electronic devices, for medical treatment and rehabilitation. In such biological implants, external data transmitters communicate control and data signals to the implant wirelessly. For example, deep brain implants are used to control seizures in epileptic patients where the external command signals may include information about pattern for micro-stimulation and feedback. At the same time the external controller is also responsible to deliver power to the implant device wirelessly. This method of power delivery is called power telemetry. Due to limited efficiency of such power delivery, it places a critical constraint on the power consumption of the embedded transceivers. In these applications, it has been found that Binary Phase Shift Keying (“BPSK”) is a more suitable protocol of communication than Amplitude Shift Keying (“ASK”) and Frequency Shift Keying (“FSK”). The reason for this is that BPSK has fixed signal amplitude and a constant carrier frequency. Constant amplitude carrier signal provides a stable power transfer at high transfer efficiency and the constant carrier frequency allows the use of fixed sized antennas designed for optimal data and power coupling. BPSK transceivers have been designed for biological implants with great success.
FIG. 1A shows a block diagram of a squaring loop design type BPSK demodulator 100. The squaring loop design 100 is one of the earliest circuits used for the detection of BPSK signals. The squaring loop design 100 includes a square device 110, a divide-by-2 frequency divider 120, and a phase lock loop (“PLL”) 130. The PLL includes a low pass filter (“LPF”) 132 and a voltage control oscillator (“VCO”) 134. The squaring loop design 100 extracts a carrier signal 140 by using the square device 110 to cancel the data riding on top of it, but in the process the square device 110 doubles the carrier frequency. Therefore, the divide-by-2 frequency divider 120 is needed to extract the carrier frequency once the phase lock loop (PLL) 130 locks onto the doubled carrier frequency.
FIG. 1B shows a block diagram of a BPSK demodulator using a Costas loop design 150. The Costas loop design is a very successful solution for coherent detection of BPSK signals. The Costas loop design includes a lower branch 160, an upper branch 170, and a center branch 180. The upper and lower branches 160, 170 include respective mixers 162, 172 and LPFs 164, 174. The center branch 180 includes a mixer 182, a LPF 184, a VCO 184, and a quadrature signal generator 188. The quadrature signal generator 188 generates two signals with identical frequency, but each signal has a 90 degree phase difference. These two signals are independently multiplied by the BPSK signal to perform down-conversion multiplications into an “I” signal and a “Q” signal. When locked, the lower branch 160 (Q branch) together with center branch 180 form a loop that acts as a normal PLL that locks onto the carrier frequency. The BPSK data information 190 is then extracted in the upper branch 170 (I branch).